Open course ware

Let us try to understand the format of the data handed to us in the CSV files. Grayscale images are represented as a matrix of pixel intensity values that range from zero to one. The intensity value zero corresponds to the absence of color, or black, and the value one corresponds to white. For 8 bits per pixel images, we have 256 color levels ranging from zero to one. For instance, if we have the following grayscale image, the pixel information can be translated to a matrix of values between zero and one. It is exactly this matrix that we are given in our datasets. In other words, the datasets contain a table of values between zero and one. And the number of columns corresponds to the width of the image, whereas the number of rows corresponds to the height of the image. In this example, the resolution is 7 by 7 pixels. We have to be careful when reading the dataset in R. We need to make sure that R reads in the matrix appropriately. Until now in this class, our datasets w...

Okay, now that we understand how to build combinational logic gates using CMOS, let's turn our attention to the timing specifications for the gates. Here's a simple circuit consisting of two CMOS inverters connected in series, which we'll use to understand how to characterize the timing of the inverter on the left. It will be helpful to build an electrical model of what happens when we change V_IN, the voltage on the input to the left inverter. If V_IN makes a transition from a digital 0 to a digital 1, the PFET switch in the pullup turns off and the NFET switch in pulldown turns on, connecting the output node of the left inverter to GROUND. The electrical model for this node includes the distributed resistance and capacitance of the physical wire connecting the output of the left inverter to the input of the right inverter. And there is also capacitance associated with the gate terminals of the MOSFETs in the right inverter. When the output node is connected ...

In order to better understand the role of each of the beta control signals, we will work through an example problem that provides us with a partially filled control table for 5 different instructions. Two of these instructions are existing beta instructions that we must infer from the provided control signals. The other three are three new instructions that we are adding to our beta by modifying the necessary control signals to produce the desired behavior of each of the operations. The first instruction that we want to add to our beta is an LDX instruction which is a load that is double indexed. What this means is that in order to produce the effective address of the load, instead of adding the contents of a register to a constant as is done in the LD instruction, we add the contents of two different registers. So the address for this load operation is the result of adding together the contents of registers Ra and Rb. The contents of the memory location pointed to by thi...

In order to understand how procedures are implemented on the beta, we will take a look at a mystery function and its translation into beta assembly code. The mystery function is shown here: The function f takes an argument x as an input. It then performs a logical AND operation on the input x and the constant 5 to produce the variable a. After that, it checks if the input x is equal to 0, and if so returns the value 0, otherwise it returns an unknown value which we need to determine. We are provided with the translation of this C code into beta assembly as shown here. We take a closer look at the various parts of this code to understand how this function as well as procedures in general work on the beta. The code that calls the procedure is responsible for pushing any arguments onto the stack. This is shown in pink in the code and on the stack. If there are multiple arguments then they are pushed in reverse order so that the first argument is always in the same location r...