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For this problem, assume that we have a computer system that has three devices D1, D2, and D3. Each of these devices can cause interrupts in our system. This table summarizes the interrupt characteristics of our three devices. For each device, we are given its service time which is the amount of time it takes to service an interrupt for that particular device. We are given an interrupt frequency which tells us how frequently the interrupts for that device arrive. You can assume that the first interrupt of each device can arrive at any time. The deadline is the longest amount of time that is allowed between the interrupt request and the completion of the interrupt handler. Assume we have a program P that takes 100 seconds to execute when interrupts are disabled. We would like to figure out how long it would take to execute this program when interrupts are enabled. To answer this question, we need to determine the amount of cpu time that is dedicated to the handling of each...

For this problem, assume that you have a fully functioning 5-stage pipelined beta with full bypassing and annulment of branch delay slots as presented in lecture. This beta has been running the program shown here for a while. The actual functionality of this program is not so important for this problem, but lets just review it quickly. This program begins by initializing R1 to 0 before entering the loop. R1 represents the index of the array element currently being accessed. Within the loop, the value of that array element is loaded into R0. R1 is then incremented by 4 in order to point to the next element in the array. We then compare the array element that was just loaded into R0 with the updated index in R1 and if they are equal, then we repeat the loop. If they are not equal, then we store the current value of R1 into a memory location called index to remember which index value satisfied the compare instruction. We want to understand how this program would run on our b...

For this problem, assume that you have discovered a room full of discarded 5-stage pipelined betas. These betas fall into four categories. The first is completely functional 5-stage Betas with full bypass and annulment logic. The second are betas with a bad register file. In these betas, all data read directly from the register file is zero. Note that if the data is read from a bypass path, then the correct value will be read. The third set are betas without bypass paths. And finally, the fourth are betas without annulment of branch delay slots. The problem is that the betas are not labeled, so we do not know which falls into which category. You come up with the test program shown here. Your plan is to single step through the program using each Beta chip, carefully noting the address that the final JMP loads into the PC. Your goal is to determine which of the four classes each chip falls into via this JMP address. Notice that on a fully functional beta, this code would ex...