5.2.2 D Latch
We can use a 2-to-1 multiplexer to build a settable storage element. Recall that a MUX selects as its output value the value of one of its two data inputs. The output of the MUX serves as the state output of the memory component. Internally to the memory component we'll also connect the output of the MUX to its D0 data input. The MUX's D1 data input will become the data input of the memory component. And the select line of the MUX will become the memory component's load signal, here called the gate. When the gate input is LOW, the MUX's output is looped back through MUX through the D0 data input, forming the bi-stable positive feedback loop discussed in the last section. Note our circuit now has a cycle, so it no longer qualifies as a combinational circuit. When the gate input is HIGH, the MUX's output is determined by the value of the D1 input, i.e., the data input of the memory component. To load new data into the memory component, we set the gate in...